1. Field of the Invention
The invention relates generally to residue free patterned layer formation. More particularly, the invention relates to residue free patterned layer formation applicable to CMOS structures.
2. Description of the Related Art
CMOS structures comprise a complementary doped pair of field effect transistor (FET) devices that include an nFET device and a pFET device. The use of complementary doped pairs of field effect transistors when fabricating CMOS structures is desirable in semiconductor fabrication since such complementary doped pairs of field effect transistors typically provide for reduced power consumption within CMOS structures.
Recent advances in CMOS structure fabrication have centered around the use of different materials, including in particular different semiconductor channel materials, different gate dielectric materials and different gate electrode materials, for fabricating nFET devices in comparison with pFET devices within CMOS structures. In general, charge carrier mobility enhancements may be effected within both nFET devices and pFET devices by a particular selection of a semiconductor substrate channel material and crystallographic orientation, including related mechanical stress effects thereon. In addition, different gate dielectric materials for nFET devices and pFET devices provide for differing capacitive effects within CMOS structures. Finally, different gate electrode materials selections for nFET devices and pFET devices within CMOS structures often provide for different work functions that in turn also influence operating characteristics of the nFET devices and the pFET devices.
The use of different materials of construction for nFET devices and pFET devices within CMOS structures clearly provides performance advantages of the nFET devices and the pFET devices within the CMOS structures. However, the use of different materials of construction for nFET devices and pFET devices within CMOS structures is clearly also not entirely without problems. In particular, the use of different materials for fabricating nFET devices and pFET devices within CMOS structures often presents difficulties with respect to efficient device fabrication, including residue free materials processing when fabricating the nFET devices and the pFET devices.
Various CMOS structures, and methods for fabrication thereof, are known in the semiconductor fabrication art.
For example, Rhee et al., in U.S. Pub. No. 2002/0113294, teaches a CMOS semiconductor structure and a method for fabricating the same that uses differing spatial distributions of the same germanium concentration within an nFET polysilicon gate electrode and a pFET polysilicon gate electrode within the CMOS structure. The differing spatial distributions of the same germanium concentration are used for addressing depletion effects within the nFET polysilicon gate electrode and the pFET polysilicon gate electrode.
In addition, Takayanagi et al., in U.S. Pat. No. 6,746,943, teaches a CMOS structure and a method for fabricating the same that includes a polysilicon-germanium alloy nFET gate electrode and a polysilicon-germanium alloy pFET gate electrode having different germanium concentrations. The different germanium concentrations allow for addressing different dopant activation properties of n dopants and p dopants within the nFET gate electrode and the pFET gate electrode within the CMOS structure.
Finally, Polischuck et al., in U.S. Pat. No. 6,794,234, teaches a CMOS structure and a method for fabricating the CMOS structure that provides an nFET gate electrode and a pFET gate electrode with different work functions within the CMOS structure. The different work functions for the nFET gate electrode and the pFET gate electrode provide for enhanced performance of the individual nFET device and pFET device within the CMOS structure.
Semiconductor device and semiconductor structure dimensions are certain to continue to decrease as semiconductor technology advances. Thus, desirable are CMOS structures, and methods for fabrication thereof, that provide nFET devices and pFET devices with enhanced performance, absent involved processing sequences that provide processing residues within the CMOS structures.